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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8021/VSC8022
Features
* Serial Data Rates up to 2.5Gb/s * Parallel Data Rates up to 312.5Mb/s * ECL 100K Compatible Parallel Data I/Os * Divide-by-8 Clock for Synchronization of Parallel Data to Interfacing Chips * SONET Frame Recovery Circuitry (VSC8022) * Compatible with STS-3 to STS-48 SONET Applications
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
* Differential or Single-Ended Inputs and Outputs * Low Power Dissipation: 2.3W (Typ Per Chip) * Standard ECL Power Supplies: VEE = -5.2V, VTT = -2.0V * Available in Commercial (0C to +70C) or Industrial (-40C to +85C) Temperature Ranges * Proven E/D Mode GaAs Technology * 52-Pin Leaded Ceramic Chip Carrier
Functional Description
The VSC8021 and VSC8022 are high-speed SONET interface devices capable of handling serial data at rates up to 2.5Gb/s. These devices can be used for STS-3 through STS-48 SONET applications. These products are fabricated in gallium arsenide using the Vitesse H-GaAs E/D MESFET process which achieves high-speed and low power dissipation. These products are packaged in a ceramic 52-pin leaded ceramic chip carrier.
VSC8021
The VSC8021 contains an 8:1 multiplexer and a self-positioning timer. The 8:1 multiplexer accepts 8 parallel differential ECL data inputs (D1-D8, D1N-D8N) at rates up to 312.5Mb/s and multiplexes them into a serial differential bit stream output (DO, DON) at rates up to 2.5Gb/s. The internal timing of the VSC8021 is built around the high-speed clock (up to 2.5GHz) delivered onto the chip through a differential input (CLKI, CLKIN). This signal is subsequently echoed at the high-speed differential output (CO, CON). The parallel data inputs are clocked to on-chip input registers with an externally supplied differential ECL input (BYCLK, BYCLKN) operating at the same rate as the data inputs. An internal byte clock, which is a divide-by-8 version of the high-speed clock, is used to transfer the data to a set of buffer registers. This internal byte clock is brought off chip at the ECL output CLK8, CLK8N. Internal circuitry monitors the internal and external byte clocks and generates an ERR signal if a timing violation is detected. This signal can be gated to the SYNC input which is edge sensitive high. An active SYNC input allows the VSC8021 timing to shift, positioning it properly against the external byte clock, CLK8, CLK8N. When a CLK8 timing switch is made, normal data flow will be invalid for 1 byte. There are two clock inputs, CLKI and BYCLK, going into the VSC8021. These two clocks serve as timing references for different parts of the VSC8021. The BYCLK is used to trigger the input registers for the parallel data inputs, while the CLKI is used to trigger the high-speed serial output register as well as some of the timing circuitry for the parallel to serial conversion. Furthermore, in order to make this part easy to use, the user is not required to assume a known phase relationship between CLKI and the BYCLK.
G52028-0, Rev 4.1 05/25/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Data Sheet
VSC8021/VSC8022
An internal Phase Detector and Phase Adjust Circuit are used to facilitate the two asynchronous circuits to work with each other. The Phase Detector and the Phase Adjust Circuit work together to adjust the internal clock CLK8 to make sure the set up and hold conditions are met for the internal registers. CLK8 is derived from CLKI and the RCLK is a non-phase varying byte clock output. The edge sensitive SYNC signal is simply the control signal that enables the Phase Detector circuitry. As a summary, the CLKI is the high-speed clock input. The BYCLK is the external byte clock. The CLK8 is the internal byte clock derived from CLKI, phase-adjusted if SYNC is enabled. The RCLK is a non-phaseadjusted divided-by-8 clock generated from CLKI. The phase of RCLK, RCLKN is not affected by the selfadjusting circuitry, therefore it can be used as a system reference clock. RCLK, RCLKN can be used by the system designer to generate BYCLK, BYCLKN. The self-positioning timer and RCLK, RCLKN allow for the creation of very tight parallel data timing for the VSC8021.
Figure 1: VSC8021 Block Diagram
D1 D1N Parallel Data D8 D8N CLK8 SYNC
Phase Adjust
8
8
8:1 Multiplexer
DO DON Serial Data Output
CLK8N
Phase Adjustable Byte Clock Output
Byte Clock Inputs
BYCLK BYCLKN
Timing Generator
RCLK RCLKN CO CON ERR
Independent Byte Clock Output
High Speed Clock Inputs
CLKI CLKIN
High Speed Clock
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52028-0, Rev 4.1 05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8021/VSC8022
VSC8022
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
The VSC8022 contains both a 1:8 demultiplexer and SONET frame recovery circuitry. The 1:8 demultiplexer accepts a serial data input (DI, DIN) at rates up to 2.5Gb/s and converts it into 8 parallel differential ECL data outputs (D1-D8, D1N-D8N) at rates up to 312.5Mb/s. Valid parallel data outputs are indicated by the divide by 8 differential clock outputs BYCKO, BYCKON. The VSC8022 also contains a SONET frame recovery circuit. The frame recovery circuits are enabled by a falling edge on the OOFN ECL input when the FDIS input is low. Once enabled, the frame recovery circuit starts looking for the SONET framing sequence. Once the frame is detected, the word boundary is realigned, a confirmation signal is sent off-chip through the FP ECL output and the frame recovery circuits are disabled. While the frame aligner is hunting for the frame, BYCKO, BYCKON and parallel data are invalid. Figure 2: VSC8022 Block Diagram
D1 D1N Serial Data In DI DIN 1:8 Demultiplexer D8 D8N Parallel Data Outputs
High Speed Clock Inputs
CLKI CLKIN
Timing Generator
Frame Recovery Disable -- FDIS Frame Recovery Clock -- OOFN
SONET Frame Detection & Recovery
FP -- Frame Detection Signal
BYCKO BYCKON Byte Clock Out
Frame recovery circuits are disabled by frame detection (resulting in FP) or by a falling edge on the OOFN input while FDIS is high.
G52028-0, Rev 4.1 05/25/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Data Sheet
VSC8021/VSC8022
VSC8021 Multiplexer AC Characteristics (Over recommended operating conditions)
Figure 3: VSC8021 Multiplexer Waveforms
tC
CLKI (1), CLKIN
High speed differential clock input tD
BYCLK (BYCLKN)
Byte clock input
(1)
CLK8
(2)
Phase adjustable /8 output tDSU tDH tBCLK8
D1-D8, D1N-D8N
Parallel differential data inputs
VALID DATA(1)
VALID DATA(2) tCMD
CO, CON
High speed differential clock outputs
DO,DON
High speed differential data outputs
D01
D02
D03
D04
D05
D06
D07
D08
SYNC
CLK8 adjustment input NOTES: (1) Negative edge is active edge. (2) BYCLK/CLK8 timing required when SYNC not connected to ERR. CLKI (CLKIN) period x 8 = BYCLK (BYCLKN) period. = Don't care.
Serialized Byte 1
Table 1: VSC8021 Multiplexer AC Characteristics (over recommended operating conditions) Parameter
tC tD tDSU tDH tCMD tBCLK8 Jitter (p-p) Clock period(1) BYTE clock period (tD = tC x 8) Parallel data set-up time Data hold time High-speed clock output (CO, CON) timing, falling edge of CO to muxed data output, (DO, DON) timing Byte clock to CLK8 timing(2) CLKI, CLKIN to DO, DON (max-min), (HI to LO), same part, same pin at constant conditions
Description
Min
400 3.2 0.6 1.4 220 0.5
Typ
Max
Units
ps ns ns ns
Conditions
350 1.0 <50 1.5
ps ns ps
NOTES: (1) The parts are guaranteed by design to operate from DC to a maximum frequency of 2.5GHz. (2) Required when SYNC not connected to ERR.
Page 4
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52028-0, Rev 4.1 05/25/01
VSC8021/VSC8022
Data Sheet
G52028-0, Rev 4.1 05/25/01
VSC8022 AC Characteristics (Over recommended operating conditions)
tC CLKI
(1)
(CLKIN) t OOFNPW t OOFN
SONET STS-3 Framing Sequence
DATA DATA DATA DATA DATA
High speed differential clock input
OOFN
Frame recovery clock input
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
DI (DIN)
High speed serial data inputs
A1
A1
A1
A2
A2
A2
Figure 4: VSC8022 Demultiplexer Waveforms
tD BYCKO (BYCKON)
Byte clock output
BYCKO Resynch
VITESSE
SEMICONDUCTOR CORPORATION
t BD
Valid Valid Valid Valid Valid Valid Valid Valid Data Data Data Data Data Data Data Data Valid Valid Valid Valid Valid Valid Valid Valid Data Data Data Data Data Data Data Data
D1 (D1N) D2 (D2N) D3 (D3N) D4 (D4N) D5 (D5N) D6 (D6N) D7 (D7N) D8 (D8N) Parallel Data* Output Summary
(2)
A1
A1 t DFP
A2
A2
A2 t PFP
Data
Data
Data
Data
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
FP
Frame detection confirm output NOTES: 1) Negative edge is active edge.
2) The parallel data outputs only begin showing valid data after the last A2 of the SONET framing sequence. The example waveforms shown above use an STS-3 framing sequence for convenience, thus valid data is output after the third A2 in the sequence. = Don't care.
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Table 2: VSC8022 Demultiplexer AC Characteristics Parameter
tC tD tBD tDFP tPFP tOOFN tOOFNPW Phase Margin Clock period
(1)
Data Sheet
VSC8021/VSC8022
Min
400 3.2 0.5 1.0 3.2 3.2 12.8 3.2 2.0
Description
BYTE clock period (tD = tC x 8) (framed) BYTE clock output to valid data FP rising edge from parallel data output change from A1 to A2 (tDFP = tD) FP pulse width (tPFP = tD) OOFN falling edge before A1 chan ges to A2 (tOOFN = tD x 4) OOFN pulse width (tOOFNPW = tD) Serial data phase timing margin with respect to high-speed clock: tSU + tH Phase Margin = 1 - ------------------ 360 tC
Typ
Max
Units
ps ns ns ns ns ns ns
Conditions
135
180
degrees
NOTE: (1) If t C changes, all the remaining parameters change as indicated by the equations.
DC Characteristics
Table 3: Low Speed ECL Inputs and Outputs
(Over recommended operating range with internal VREF, VCC = GND, output load = 50 to -2.0V)
Parameter
VOH VOL VIH VIL VOUT
Description
Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Output voltage swing
Min
-1020 VTT -1150 VTT 0.8
Typ
Max
-700 -1620 -600 -1500
Units
mV mV mV mV V
Conditions
VIN = VIH (max) or VIL (min) VIN = VIH (max) or VIL (min) Guaranteed HIGH signal for all inputs Guaranteed LOW signal for all inputs Output load 50 to VTT
1.0
1.4
Note: Differential ECL output pins must be terminated identically.
Table 4: High-Speed Inputs and Outputs
(Over recommended operating conditions, VCC = GND, Output load = 50 to -2.0V)
Parameter
VIN VOH VOL VOUT(DATA) VOUT(clk)
Description
Input voltage swing Output HIGH voltage Output LOW voltage Output voltage swing for data Output voltage swing for clock
Min
0.8
Typ
1.0 -0.9 -1.8
Max
1.2
Units
V V V
Conditions
AC-coupled Output load, 50 to -2.0V Output load, 50 to -2.0V Output load, 50 to -2.0V Output load, 50 to -2.0V
0.6 0.6
0.8 0.7
1.2 1.2
V V
NOTES: (1) A reference generator is built in to each high-speed input, and these inputs are designed to be AC-coupled. (2) If a high-speed input is used single-ended, a 150pF capacitor must be connected between the unused high-speed or complement input and the power supply (VTT). (3) Differential high-speed outputs must be terminated identically.
Page 6
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52028-0, Rev 4.1 05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8021/VSC8022
Table 5: Power Dissipation
(Over recommended operating conditions, VCC = GND, outputs open circuit)
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
VSC8021 Parameter
IEE ITT PD
VSC8022 Units Conditions Max
600 200 3.75
Description Min
Power supply current from VEE Power supply current from VTT Power dissipation
Typ
400 110 2.3
Min
Typ
450 120 2.6
Max
600 200 3.75
mA mA W
Absolute Maximum Ratings(1)
Power Supply Voltage (VTT) ..........................................................................................................-3.0V to + 0.5V Power Supply Voltage (VEE) .................................................................................................. VTT + 0.7V to -6.0V ECL Input Voltage Applied(2) (VECLIN) ........................................................................................-2.5V to + 0.5V High-Speed Input Voltage Applied(2) (VHSIN)............................................................... VEE -0.7V to VCC + 0.7V Output Current (DC, output HIGH) (IOUT).................................................................................................-50 mA Case Temperature Under Bias (TC)...............................................................................................-55C to +125C Storage Temperature(3) (TSTG)......................................................................................................-65C to +150C
Recommended Operating Conditions
ECL Power Supply Voltage(4) (VTT).................................................................................................. -2.0V 0.1V Power Supply Voltage (VEE) ............................................................................................................ -5.2V 0.26V Operating Temperature Range(3) (T)............................. (Commercial) 0C to +70C, (Industrial) -40C to +85C
Notes: (1) Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) VTT must be applied before any input signal voltage magnitude (VECLIN and VHSIN) can be greater than VTT -0.5V. (3) Lower limit of specification is ambient temperature and upper limit is case temperature. (4) When using internal ECL 100K reference level.
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC8021/VSC8022 is rated to the following ESD voltages based on the human body model: 1. All ECL pins are rated at or above 1000V. 2. All high-speed clock and data pins at rated at or above 500V.
G52028-0, Rev 4.1 05/25/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Data Sheet
VSC8021/VSC8022
VSC8022 SONET Frame Recovery and Detection
The SONET framing sequence is a string of A1 bytes followed by a string of A2 bytes. (A1 = 11110110 and A2 = 00101000). The first serial bit starts at the left of the byte. Table 6 shows the number of A1 and A2 bytes in each SONET frame for different line rates. The VSC8022 contains a frame recovery circuit and a frame detection circuit. Table 6: A1/A2 Byte Count STS Level
STS-3 STS-12 STS-48
Line Rate (Mb/s)
155.520 622.080 2488.32
# of A1 Bytes
3 12 48
# of A2 Bytes
3 12 48
Frame Recovery Circuit The frame recovery circuit is designed to scan the serial data stream, looking for the A1 byte. When it finds the A1 pattern, it adjusts internal timing so that the serial data is properly demultiplexed onto the eight parallel outputs. Subsequently, the MSB of the A1 byte will appear in the D1 position and LSB of the A1 byte will appear in the D8 position. This word boundary alignment causes the BYCKO, BYCKON output to be resynchronized. While the frame aligner is hunting for the frame, BYCKO and parallel data are invalid. Frame recovery circuits are disabled by frame detection (resulting in FP) or by a falling edge on the OOFN input while FDIS is high. Frame Detection Circuit The frame detection circuit monitors the demultiplexed data, and senses the boundary between A1 and A2 bytes. This pulse on the FP output will reset the frame recovery circuit, so that no further resynchronization will occur until permission is given through OOFN. Circuit Operation The frame recovery circuits are initialized and enabled on the falling edge of the OOFN ECL input with FDIS held low. The OOFN must be at least one byte clock period wide. It must occur at least four byte clock periods before the A1/A2 boundary. The circuit requires at least three A1 bytes followed by 3 A2 bytes for successful alignment. The first A1 byte is used by the frame recovery circuit to obtain initial word boundary alignment, while the following two A1 and three A2 bytes are used to reset the frame recovery circuit and maintain alignment for the subsequent bit stream. Frame recognition will occur for each word boundary aligned A1A1A2A2A2 sequence in the data stream. Frame recognition is signaled by a one byte clock period high pulse on the FP ECL output pin. This FP pulse will appear one byte period after the first A2 byte appears on the parallel data output pins.
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52028-0, Rev 4.1 05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8021/VSC8022
Figure 5: SONET Frame Structure
STS-3 Frame 125s 3 x 90 Bytes 3 x 3 Bytes 3 A1s 9 Rows 3 A2s 3 C1s 9 Rows 3 x 48 Bytes 48 A1s 48 A2s
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
STS-48 Frame 125s 48 x 90 Bytes
48 C1s
DATA
DATA
Transport Overhead
STS-3 Envelope Capacity
Transport Overhead
STS-48 Envelope Capacity
A1s and A2s: SONET Framing Sequence C1s: STS Frame ID
High-Speed Inputs In the past, the high-speed inputs, which are typically used for serial data and high-speed clock inputs with frequencies greater than 1GHz, were specified with absolute minimum and maximum voltage values. Since these inputs are intended for AC-coupled applications, they have been re-specified in terms of a voltage swing (VIN). High-speed clocks are intended for AC-coupled operation. In most situations high-speed serial data will have high transition density and contain no DC offsets, making them candidates for AC-coupling as well. However, it is possible to employ DC-Pcoupling when the serial input data contains a DC component. The structure of the high-speed input circuit is shown in Figure 6. DC-coupled circuits may be used to operate this input provided that the input swing is centered around the reference voltage. It is recommended that, in single-ended DC-coupling situations, the user provide an external reference which has better temperature and power supply rejection than the simple on-chip voltage divider. This external reference should have a nominal value of -3.5V and can be connected to the complementary input. This complication can be avoided in DC-coupled situations by using differential signals. Figure 6: High-Speed Input Circuit Structure
Chip Boundary VCC = GND
150 pF
-3.5 V
-3.5 V R * 1k*
50* VTT 150 pF
VTT
VEE = -5.2V
G52028-0, Rev 4.1 05/25/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Figure 7: VSC8021 Pin Diagram
Heat Sink Up Top View
CLK8N
Data Sheet
VSC8021/VSC8022
SYNC 28
CLK8
VCC
VCC
ERR
VEE
D2N
DIN
39
38
37
36
35
34
33
32
31
30
29
D3N D4 D4N VCC BYCLK BYCLKN VTT D5 D5N VCC D6 D6N D7
27
NC
D3
D2
DI
40 41 42 43 44 45 46 47 48 49 50 51 52
26 25 24 23 22 21
NC NC DON VEE DO CO CON CLKIN VCC CLKI NC NC NC
VSC8021 Heat Sink Side
20 19 18 17 16 15 14
1
2
3
4
5
6
7
8
9
10
11
12 NC
VCC
VTT
NC
NC
VCC
NC
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(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
RCLKN
RCLK
D7N
D8N
NC
D8
13
G52028-0, Rev 4.1 05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8021/VSC8022
Table 7: VSC8021 Pin Identifications Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Signal Name
D7N D8 D8N VCC NC RCLKN VTT RCLK NC VCC NC NC NC NC NC NC CLKI VCC CLKIN CON CO DO VEE(1) DON NC NC NC SYNC ERR VCC CLK8N CLK8
I/O
I I I Pwr
Level Type
ECL ECL ECL 0V
Description
Parallel Data Bit 7, Complement Parallel Data Bit 8, True Parallel Data Bit 8, Complement Ground No Connection
O Pwr O
ECL -2.0V ECL
Independent CLK Divide-by-8 Clock, Complement Power Supply for Internal Reference Generation and Low Power Logic Independent CLK Divide-by-8 Clock, True No Connection
Pwr
0V
Ground No Connection No Connection No Connection No Connection No Connection No Connection
I Pwr I O O O Pwr O
HS 0V HS HS HS HS -5.2V OHS
High-Speed Clock, True Ground High-Speed Clock, Complement High-Speed Clock, Complement High-Speed Clock, True High-Speed Serial Data Output, True Power Supply for High-Speed Logic High-Speed Data, Complement No Connection No Connection No Connection
I O Pwr O O
ECL ECL 0V ECL ECL
Error Correction Error Detection Ground Phase-Adjustable CLK Divide-by-8 Clock, Complement Phase-Adjustable CLK Divide-by-8 Clock, True
G52028-0, Rev 4.1 05/25/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
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VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 VEE D1 D1N VCC D2 D2N D3 D3N D4 D4N VCC BYCLK BYCLKN VTT D5 D5N VCC D6 D6N D7 Pwr I I Pwr I I I I I I Pwr I I Pwr I I Pwr I I I -5.2V ECL ECL 0V ECL ECL ECL ECL ECL ECL 0V ECL ECL -2.0V ECL ECL 0V ECL ECL ECL
Data Sheet
VSC8021/VSC8022
Power Supply for High-Speed Logic Parallel Data Bit 1, True Parallel Data Bit 1, Complement Ground Parallel Data Bit 2, True Parallel Data Bit 2, Complement Parallel Data Bit 3, True Parallel Data Bit 3, Complement Parallel Data Bit 4, True Parallel Data Bit 4, Complement Ground Divide-by-8 Clock, True Divide-by-8 Clock, Complement Power Supply for Internal Reference and Low Power Logic Parallel Data Bit 5, True Parallel Data Bit 5, Complement Ground Parallel Data Bit 6, True Parallel Data Bit 6, Complement Parallel Data Bit 7, True
NOTE: (1) Pin #23 is connected to the heat sink. Connect to VEE or most negative chip voltage.
Page 12
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52028-0, Rev 4.1 05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8021/VSC8022
Figure 8: VSC8022 Pin Diagram
Heat Sink Up Top View
VCC VCC VEE D6N D7N D8N NC NC NC 28
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
39
38
37
36
35
34
33
32
31
30
29
D5N NC D5 VCC BYCKON NC VTT BYCKO D4N VCC D4 D3N D3
27
NC
D6
D7
D8
40 41 42 43 44 45 46 47 48 49 50 51 52
26 25 24 23 22 21
NC NC NC VEE NC NC NC CLKIN VCC CLKI DIN DI NC
VSC8022 Heat Sink Side
20 19 18 17 16 15 14
1
2
3
4
5
6
7
8
9
10
11
12 OOFN
VTT
FP
FDIS
VCC
NC
NC
D2
VCC
D2N
D1N
NC
D1
13
G52028-0, Rev 4.1 05/25/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 13
VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Table 8: VSC8022 Pin Identifications Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Data Sheet
VSC8021/VSC8022
Level Type
No Connection No Connection O ECL 0V ECL ECL -2.0 ECL ECL 0V ECL ECL Parallel Data Bit 2, Complement Ground Parallel Data Bit 2, True Parallel Data Bit 1, Complement Power Supply for Internal Reference Generation and Low Power Logic Parallel Data Bit 1, True Frame Pulse. This pulse will appear one byte period after the first A2 byte appears on the parallel data output pins. Ground Frame Recovery Disable Frame Recovery Enable No Connection No Connection I I I HS HS HS 0V HS High-Speed Serial Data Bit 1, True High-Speed Serial Data Bit 1, Complement High-Speed Clock, True Ground High-Speed Clock, Complement No Connection No Connection No Connection
Signal Name
NC NC D2N VCC D2 D1N VTT D1 FP VCC FDIS OOFN NC NC DI DIN CLKI VCC CLKIN NC NC NC VEE(1) NC NC NC NC NC NC VCC D8N
I/O
Description
Pwr O O Pwr O O Pwr I I
Pwr I
Pwr
-5.2V
Power Supply for High-Speed Logic No Connection No Connection No Connection No Connection No Connection No Connection
Pwr O
0V ECL
Ground Parallel Data Bit 8, Complement
Page 14
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52028-0, Rev 4.1 05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8021/VSC8022
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 D8 VEE D7N D7 VCC NC D6N D6 D5N NC D5 VCC BYCKON NC VTT BYCKO D4N VCC D4 D3N D3 Pwr O O Pwr O O O -2.0V ECL ECL 0V ECL ECL ECL O Pwr O ECL 0V ECL O O O ECL ECL ECL O Pwr O O Pwr ECL -5.2V ECL ECL 0V Parallel Data Bit 8, True
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Power Supply for High-Speed Logic Parallel Data Bit 7, Complement Parallel Data Bit 7, True Ground No Connection Parallel Data Bit 6, Complement Parallel Data Bit 6, True Parallel Data Bit 5, Complement No Connection Parallel Data Bit 5, True Ground Divide-by-8 Clock, Complement No Connection Power Supply for Internal Reference and Low Power Logic Divide-by-8 Clock, True Parallel Data Bit 4, Complement Ground Parallel Data Bit 4, True Parallel Data Bit 3, Complement Parallel Data Bit 3, True
NOTE: (1) Pin #23 is connected to the heat sink. Connect to VEE or most negative chip voltage.
G52028-0, Rev 4.1 05/25/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 15
VITESSE
SEMICONDUCTOR CORPORATION
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
Data Sheet
VSC8021/VSC8022
52-Pin Leaded Ceramic Package (LDCC)
Package Information
B
D
HEAT SINK SIDE PACKAGE IS CAVITY DOWN
52
E
45
1
N A C
O I J
K
L
M
NOTES: Drawing not to scale. Packages: Ceramic (alumina); Heat sink: Copper-tungsten; Leads: Alloy 42 with gold plating.
Item
A B C(1) D(1) E F G H
mm (Min/Max)
18.54/19. 56 1.02/1.52 15.49/16.51 15.24 TYP 1.27 TYP 0.76/1.02 16.94 TYP 1.91/2.41
in (Min/Max)
0.730/0.770 0.040/0.060 0.610/0.650 0.600 TYP 0.050 TYP 0.030/0.040 0.667 TYP 0.075/0.095
Item
I J K(1) L M N O --
mm (Min/Max)
0.41/0.61 2.03/2.79 0.09/0.24 4.57/5.34 27.69/30.22 0.36/0.56 1.75/1.90 --
in (Min/Max)
0.016/0.024 0.080/0.110 0.003/0.009 0.180/0.210 1.090/1.190 0.014/0.022 0.069/0.075 --
NOTE: (1) At package body.
Page 16
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
G52028-0, Rev 4.1 05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8021/VSC8022
Order information
2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
The order number for this product is formed by a combination of the device number, and package type.Notice
VSC802x Device Type
VSC8021: SONET 2.5Gb/s 8-Bit Multiplexer VSC8022: SONET 2.5Gb/s 8-Bit Demultiplexer
X
X
Temperature C: Commercial (0C to +70C) I: Industrial (-40C to +85C) Package F: Ceramic Leaded Chip Carrier (LDCC)
Notice
Vitesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
G52028-0, Rev 4.1 05/25/01
(c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com
Page 17

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